Bridging RTL and Assertion Generation With Large Language Models

Editor’s notes: This article presents a unified, resource-efficient framework that leverages large language models to jointly automate RTL generation and SystemVerilog assertion synthesis, overcoming long-standing fragmentation between design and verification. By fine-tuning LLaMA2-7B with LoRA/QLoRA and deriving assertions directly from generated RTL, the authors demonstrate substantial gains in correctness, consistency, and practicality for modern EDA workflows. –Arnab Raha, Intel, USA